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A Generic Methodology to Compute Design Sensitivity to SEU in SRAM-Based FPGA.

Mahsa MousaviHamid Reza PourshaghaghiMohammad TahghighiRoel JordansHenk Corporaal
Published in: DSD (2018)
Keyphrases
  • design methodology
  • high level
  • hardware design
  • real time
  • building blocks
  • design process
  • power consumption
  • conceptual model
  • power reduction
  • application specific
  • hardware architecture
  • verilog hdl