Intel® Core™ i5/i7 QuickPath Interconnect receiver clocking circuits and training algorithm.
Nasirul ChowdhuryJeff WightChristopher MozakNasser A. KurdPublished in: VLSI-DAT (2012)
Keyphrases
- training algorithm
- power dissipation
- circuit design
- high speed
- back propagation
- neural network
- training process
- low power
- conjugate gradient
- neural network training
- power consumption
- learning rate
- learning algorithm
- rbf neural network
- support vector machine
- gradient vector
- machine learning
- hidden layer
- digital signal processing
- feed forward
- training data
- radial basis function
- bp algorithm
- rough sets
- pairwise
- training set
- artificial intelligence
- data mining