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Formal Verification of Timed VHDL Programs.
Abdelrezzak Bara
Pirouz Bazargan-Sabet
Remy Chevallier
Dominique Le Dû
Emmanuelle Encrenaz
Patricia Renault
Published in:
FDL (2010)
Keyphrases
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formal verification
program slicing
model checking
timed automata
bounded model checking
finite state machines
automated verification
petri net
model checker
symbolic model checking
model based diagnosis
temporal logic
hardware implementation
computer programs
efficient implementation