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An Evaluation of Selective Depipelining for FPGA-Based Energy-Reducing Irregular Code Coprocessors.

Jack SampsonManish AroraNathan Goulding-HottaGanesh VenkateshJonathan BabbVikram BhattSteven SwansonMichael Bedford Taylor
Published in: FPL (2011)
Keyphrases
  • hardware implementation
  • source code
  • energy consumption
  • evaluation method
  • real time
  • neural network
  • web services
  • evolutionary algorithm
  • smart card
  • evaluation criteria
  • video processing
  • field programmable gate array