DRACO: Co-Optimizing Hardware Utilization, and Performance of DNNs on Systolic Accelerator.
Nandan Kumar JhaShreyas RavishankarSparsh MittalArvind KaushikDipan MandalMahesh ChandraPublished in: ISVLSI (2020)
Keyphrases
- field programmable gate array
- low cost
- hardware and software
- hardware implementation
- hardware architecture
- computer systems
- real time
- parallel implementation
- computing systems
- image processing
- knowledge base
- high end
- computer vision
- data mining
- real world
- graphics hardware
- computing power
- parallel hardware
- hardware design
- systolic array
- processing units
- computer architecture
- massively parallel
- personal computer
- embedded systems
- data acquisition
- information systems
- neural network