A novel frame reordering scheme and a high speed VLSI architecture of multiple reference frame motion estimator for H.264/AVC.
Kyeong-Yuk MinJong-Wha ChongPublished in: IEEE Trans. Consumer Electron. (2009)
Keyphrases
- reference frame
- motion estimation
- motion estimator
- low complexity
- vlsi architecture
- variable block size
- macroblock
- high speed
- inter frame
- video coding
- motion vectors
- low power
- rate distortion
- video codec
- mode decision
- coding efficiency
- motion field
- motion compensated
- vlsi implementation
- motion compensation
- video sequences
- motion estimation algorithm
- computational complexity
- video compression
- image sequences
- compressed domain
- optical flow
- block matching
- video coding standard
- real time
- spatial domain
- motion model
- three dimensional
- computer vision
- video streaming
- transform domain
- power consumption
- video coder
- low bit rate