A novel implementation of combined systolic and folded architectures for adaptive filters in FPGA.
Gomathi SwaminathanG. MurugesanS. SasikalaL. MuraliPublished in: Microprocess. Microsystems (2020)
Keyphrases
- hardware implementation
- fpga technology
- hardware architecture
- low cost
- digital signal processors
- systolic array
- fpga hardware
- design methodologies
- efficient implementation
- parallel architecture
- software implementation
- single chip
- real time image processing
- layered architecture
- dedicated hardware
- architectural model
- reconfigurable hardware
- hardware architectures
- implementation issues
- signal processing
- data sets