Speeding up combinational synthesis in an FPGA cluster.
César PedrazaJavier CastilloJosé Ignacio MartínezPablo HuertaJosé Luis BosqueJavier CanoPublished in: PARCO (2009)
Keyphrases
- clustering algorithm
- high speed
- hardware implementation
- data clustering
- neural network
- data points
- low cost
- hierarchical clustering
- real time
- subspace clustering
- program synthesis
- pairwise
- data acquisition
- hierarchical structure
- image processing
- data objects
- field programmable gate array
- hardware architecture
- overlapping clusters
- fpga technology