A 500-MS/s 8-b Low Power High Speed Asynchronous SAR ADC in 40-nm CMOS.
Bowen DingPeng MiaoFei LiPublished in: ICFSP (2019)
Keyphrases
- low power
- high speed
- cmos technology
- nm technology
- delay insensitive
- single chip
- analog to digital converter
- wide dynamic range
- low voltage
- mixed signal
- high power
- power reduction
- low cost
- image sensor
- power consumption
- power dissipation
- wireless transmission
- vlsi circuits
- sar images
- silicon on insulator
- digital signal processing
- low power consumption
- vlsi architecture
- logic circuits
- frame rate
- real time
- cmos image sensor
- ultra low power