A low power architecture for online detection of execution errors in SMT processors.
Rance RodriguesSandip KunduPublished in: DFTS (2013)
Keyphrases
- low power
- signal processor
- vlsi architecture
- power consumption
- low cost
- high speed
- mixed signal
- single chip
- real time
- cmos technology
- high power
- power reduction
- digital signal processing
- vlsi circuits
- parallel execution
- nm technology
- logic circuits
- multithreading
- data flow
- low power consumption
- parallel processing
- image sensor
- wireless transmission
- parallel algorithm
- cmos image sensor
- gate array
- power saving
- power dissipation
- design considerations
- parallel computing
- hardware and software
- signal processing