A Reconfigurable Hardware Architecture for Fractional Pixel Interpolation in High Efficiency Video Coding.
Cláudio Machado DinizMuhammad ShafiqueSergio BampiJörg HenkelPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2015)
Keyphrases
- hardware architecture
- hardware implementation
- high efficiency video coding
- field programmable gate array
- video coding
- hardware architectures
- multiview video coding
- signal processing
- coding method
- efficient implementation
- image processing algorithms
- processing elements
- input image
- associative memory
- low cost
- coding scheme
- parallel computing
- embedded systems
- xilinx virtex
- motion estimation
- motion vectors
- real time