A Low Power and High Speed Viterbi Decoder Based on Deep Pipelined, Clock Blocking and Hazards Filtering.
C. ArunV. RajamaniPublished in: Int. J. Commun. Netw. Syst. Sci. (2009)
Keyphrases
- low power
- high speed
- power consumption
- noisy channel
- hidden markov models
- real time
- high power
- low complexity
- digital signal processing
- frame rate
- single chip
- low cost
- wireless transmission
- error concealment
- decoding algorithm
- low power consumption
- vlsi architecture
- power reduction
- logic circuits
- vlsi circuits
- cmos technology
- image sensor
- video sequences
- low voltage
- data flow
- parallel processing