A Low-Power Spike Detector Using In-Memory Computing for Event-based Neural Frontend.
Ye KeArindam BasuPublished in: ISCAS (2024)
Keyphrases
- low power
- high speed
- low cost
- power consumption
- spike trains
- single chip
- high power
- associative memory
- spiking neurons
- vlsi architecture
- network architecture
- digital signal processing
- wireless transmission
- low power consumption
- vlsi circuits
- logic circuits
- power dissipation
- neural network
- event driven
- random access
- power reduction
- mixed signal
- nm technology
- gate array
- cmos technology
- computational power
- back end
- wireless networks
- signal processor