Low Power Instruction Cache with Word Selective Line Buffer.
Hyun-Bum ChoJu Hee ChoiSeong-Tea JhangChu-Shik JhonPublished in: CSE (2012)
Keyphrases
- low power
- memory hierarchy
- power consumption
- low cost
- high speed
- cache misses
- replacement policy
- memory access
- virtual memory
- single chip
- high power
- vlsi circuits
- low power consumption
- vlsi architecture
- wireless transmission
- prefetching
- instruction set
- main memory
- digital signal processing
- image sensor
- logic circuits
- query processing
- hardware and software
- cmos technology
- database systems
- gate array