Low power noise immune node voltage comparison keeper design for high speed architectures.
R. KannanR. RangarajanPublished in: Microprocess. Microsystems (2020)
Keyphrases
- low power
- high speed
- single chip
- power consumption
- low power consumption
- low cost
- vlsi architecture
- logic circuits
- cmos technology
- energy dissipation
- gate array
- digital signal processing
- ultra low power
- wireless transmission
- power reduction
- power dissipation
- high power
- mixed signal
- frame rate
- design process
- nm technology
- cmos image sensor
- low voltage
- design considerations
- noise model
- image processing
- real time