Login / Signup
Design and Evaluation of a Power-Efficient Approximate Systolic Array Architecture for Matrix Multiplication.
Haroon Waris
Chenghua Wang
Weiqiang Liu
Fabrizio Lombardi
Published in:
SiPS (2019)
Keyphrases
</>
systolic array
software architecture
data flow
reconfigurable architecture
user interface
power consumption
parallel architecture
power dissipation
image segmentation
bayesian networks
design methodology
matrix multiplication