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Diminution of power in load/store queue for CAM and SRAM-based out-of-order processors.

G. DhanalakshmiM. SundarambalK. Muralidharan
Published in: Int. J. Adv. Intell. Paradigms (2020)
Keyphrases
  • power consumption
  • steady state
  • load balancing
  • low power
  • queue length
  • power reduction