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FPGA Design of an Intra 16 × 16 Module for H.264/AVC Video Encoder.

Hassen LoukilImen WerdaNouri MasmoudiAhmed Ben AtitallahPatrice Kadionik
Published in: Circuits Syst. (2010)
Keyphrases
  • video encoder
  • verilog hdl
  • low complexity
  • video coding
  • motion estimation
  • computational load
  • real time
  • computational complexity
  • video codec