A 14b 100MS/s digitally self-calibrated pipelined ADC in 0.13µm CMOS.

Peter Bogner Franz Kuttner Claus Kropf Thomas Hartig Markus Burian Hermann Eul

Published in: ISSCC (2006)

Keyphrases

analog to digital converter
dynamic range
wide dynamic range
single chip
low cost
image sensor
high speed
power consumption
multi view
data flow
low power
stereo camera
circuit design
power supply
analog vlsi
pac man
cmos image sensor
low voltage
hd video
vlsi circuits
linear array
image processing