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A heuristic covering technique for optimizing average-case delay in the technology mapping of asynchronous burst-mode circuits.
Peter A. Beerel
Wei-Chun Chou
Kenneth Y. Yun
Published in:
EURO-DAC (1996)
Keyphrases
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average case
worst case analysis
worst case
uniform distribution
learning curves
delay insensitive
tabu search
cmos technology
average case complexity
machine learning
upper bound
supervised learning
vc dimension
asynchronous circuits
high level synthesis