Utilizing Valley-Spin Hall Effect in WSe2 for Low Power Non-Volatile Flip-Flop Design.
K. ChoSandeep Krishna ThirumalaX. LiuNiharika ThakuriaZhihong ChenSumeet Kumar GuptaPublished in: DRC (2020)
Keyphrases
- low power
- power dissipation
- power consumption
- cmos technology
- single chip
- low cost
- low power consumption
- high speed
- logic circuits
- digital signal processing
- vlsi architecture
- gate array
- high power
- ultra low power
- wireless transmission
- data storage
- design process
- mixed signal
- vlsi circuits
- flip flops
- efficient implementation
- power reduction