FPGA/DSP-based implementation of a high-performance multi-channel counter.
Federico BarontiAndrea LazzeriRoberto RoncellaRoberto SalettiPublished in: J. Syst. Archit. (2009)
Keyphrases
- multi channel
- signal processing
- verilog hdl
- hardware implementation
- single channel
- anti aliasing
- hardware architecture
- digital signal processing
- real time image processing
- hardware architectures
- high speed
- software implementation
- systolic array
- low power consumption
- low cost
- digital signal
- hardware design
- mac protocol
- prior knowledge
- parallel architecture
- channel assignment
- xilinx virtex
- field programmable gate array
- efficient implementation
- digital signal processors