A 9-16Gb/s clock and data recovery circuit with three-state phase detector and dual-path loop architecture.
Afshin RezayeeKenneth MartinPublished in: ESSCIRC (2003)
Keyphrases
- high speed
- data analysis
- data sets
- data points
- database
- statistical analysis
- training data
- data structure
- input data
- image data
- management system
- data collection
- data mining techniques
- knowledge discovery
- prior knowledge
- state space
- small number
- data sources
- xml documents
- web services
- databases
- sensor data
- experimental data
- data distribution
- data acquisition
- original data
- data quality
- normal operation