Performance Evaluation of RISC-Based Memory-Centric Processor Architecture.
Danijela EfnushevaPublished in: CSOC (3) (2020)
Keyphrases
- instruction set
- memory access
- level parallelism
- memory subsystem
- memory management
- processing elements
- hardware architecture
- computation intensive
- memory hierarchy
- application specific
- instruction set architecture
- computer architecture
- floating point
- high speed
- parallel architecture
- multithreading
- real time
- computing power
- embedded systems
- parallel processing
- computational power
- intel xeon
- general purpose
- multi processor
- associative memory
- random access memory
- hardware implementation
- management system
- data access
- memory requirements
- main memory
- operating system
- user centric