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A Scalable Solution to Soft Error Tolerant Circuit Design Using Partitioning-Based Gate Sizing.
M. Amin Sabet
Behnam Ghavami
Mohsen Raji
Published in:
IEEE Trans. Reliab. (2017)
Keyphrases
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error tolerant
circuit design
graph matching
data model
closed form
neural network
optimal solution
subgraph isomorphism