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A 3.3V 14-bit 125MS/s pipeline ADC with hybrid 1.8V/3.3V MOSFET technique in 0.18µm CMOS.
Xiaodan Zhou
Weipeng He
Dongbing Fu
Jianan Wang
Guangbing Chen
Published in:
IEICE Electron. Express (2024)
Keyphrases
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analog to digital converter
random access memory
low power
image sensor
low cost
high speed
mixed signal
neural network
pipeline architecture
processing pipeline
single chip
image processing
hybrid approaches
circuit design
video camera
analog vlsi
real time