Evaluation of a Low-Power Reconfigurable DSP Architecture.
Arthur AbnousKatsunori SenoYuji IchikawaMarlene WanJan M. RabaeyPublished in: IPPS/SPDP Workshops (1998)
Keyphrases
- low power
- low cost
- digital signal processing
- high speed
- vlsi architecture
- power consumption
- systolic array
- mixed signal
- power reduction
- low power consumption
- cmos technology
- single chip
- real time
- data flow
- nm technology
- high power
- logic circuits
- signal processor
- vlsi circuits
- hardware implementation
- wireless transmission
- image sensor
- signal processing
- digital signal
- embedded systems
- delay insensitive
- hardware and software
- design methodology
- power saving
- digital camera
- field programmable gate array
- texas instruments
- power dissipation