Low-power Programmable Processor for Fast Fourier Transform Based on Transport Triggered Architecture.
Jakub ZádníkJarmo TakalaPublished in: CoRR (2019)
Keyphrases
- low power
- single chip
- high speed
- vlsi architecture
- low cost
- signal processor
- power consumption
- cmos image sensor
- gate array
- cmos technology
- high power
- wireless transmission
- mixed signal
- low power consumption
- real time
- power management
- digital signal processing
- image sensor
- instruction set
- logic circuits
- hardware and software
- nm technology
- general purpose processors
- ultra low power
- embedded systems
- delay insensitive
- power reduction
- parallel processing
- low complexity
- general purpose