Design and implementation of a 16 by 16 low-power two's complement multiplier.
Alexander GoldovskyBimal PatelMichael SchulteRavi K. KolagotlaHosahalli SrinivasGeoffrey BurnsPublished in: ISCAS (2000)
Keyphrases
- low power
- vlsi architecture
- power consumption
- cmos technology
- single chip
- low cost
- low power consumption
- high speed
- digital signal processing
- ultra low power
- logic circuits
- gate array
- power dissipation
- high power
- circuit design
- design methodology
- vlsi implementation
- hardware implementation
- efficient implementation
- vlsi circuits
- image sensor
- design considerations
- real time
- power reduction
- mixed signal