A low-power 28 Gb/s CDR using artificial lc transmission line technique in 65 nm CMOS.
Shita GuoTianzuo XiGuoying WuTianwei LiuTao ZhangPing GuiYanli FanMark MorganPublished in: MWSCAS (2014)
Keyphrases
- low power
- transmission line
- cmos technology
- high speed
- nm technology
- power consumption
- low cost
- power system
- vlsi circuits
- single chip
- mixed signal
- low voltage
- image sensor
- vlsi architecture
- differential equations
- power dissipation
- magnetic field
- logic circuits
- power reduction
- delay insensitive
- silicon on insulator
- low power consumption
- ultra low power
- gate array
- real time
- operating conditions
- cmos image sensor
- neural network