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Energy and switch area optimizations for FPGA global routing architectures.
Yi Zhu
Yuanfang Hu
Michael B. Taylor
Chung-Kuan Cheng
Published in:
ACM Trans. Design Autom. Electr. Syst. (2009)
Keyphrases
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high speed
energy consumption
routing protocol
field programmable gate array
interconnection networks
real time
neural network
low cost
energy minimization
energy aware
switched networks
packet switching
routing algorithm
energy efficiency
routing problem
global information