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A precise sample-and-hold circuit topology in CMOS for low voltage applications with offset voltage self correction.

Luis Henrique de Carvalho FerreiraRobson L. MorenoTales C. PimentaCarlos A. R. Filho
Published in: ICECS (2002)
Keyphrases
  • low voltage
  • cmos technology
  • design considerations
  • power line
  • random access memory
  • power management
  • low power