UVM based STBUS verification IP for verifying SoC architectures.

Pranay Samanta Deepak Chauhan Sujay Deb Piyush Kumar Gupta

Published in: VDAT (2014)

Keyphrases

model checking
verification method
temporal logic
formal verification
formal specification
neural network
hardware and software
face verification
formal methods
genetic algorithm
multimedia
low power
signature verification
ip address
internet protocol