High performance collective communication-aware 3D Network-on-Chip architectures.

Biresh Kumar Joardar Karthi Duraisamy Partha Pratim Pande

Published in: DATE (2018)

Keyphrases

network on chip
interconnection networks
packet switched
routing algorithm
fault tolerant
parallel computers
multistage
multi processor
image processing
computer networks
communication networks
data acquisition
network simulator