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A 0.25-0.4V, Sub-0.11mW/GHz, 0.15-1.6GHz PLL Using an Offset Dual-Path Loop Architecture with Dynamic Charge Pumps.
Zhao Zhang
Guang Zhu
C. Patrick Yue
Published in:
VLSI Circuits (2019)
Keyphrases
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high speed
power consumption
frequency band
real time
software architecture
dual band
dynamic environments
management system
dielectric constant
intel xeon