Glitch-Optimized Circuit Blocks for Low-Power High-Performance Booth Multipliers.
Anuradha Chathuranga RanasingheSabih H. GerezPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2020)
Keyphrases
- low power
- high speed
- logic circuits
- low power consumption
- signal processor
- cmos technology
- power reduction
- power consumption
- gate array
- power dissipation
- low cost
- delay insensitive
- vlsi circuits
- single chip
- high power
- digital signal processing
- mixed signal
- vlsi architecture
- wireless transmission
- circuit design
- low voltage
- information flow
- real time
- nm technology
- dct coefficients
- image sensor