Design optimisation of multiplier-free parallel pipelined FFT on field programmable gate array.
Prasanna Kumar GodiBattula Tirumala KrishnaPushpa KotipalliPublished in: IET Circuits Devices Syst. (2020)
Keyphrases
- hardware implementation
- hardware architecture
- field programmable gate array
- fpga device
- programmable logic
- case study
- floating point
- parallel processing
- embedded systems
- hardware design
- image processing
- artificial intelligence
- probabilistic model
- scheduling problem
- access control
- user interface
- design methodology
- massively parallel
- computer architecture
- real time