Low-power LDPC decoder design exploiting memory error statistics.
Junlin ChenLei WangPublished in: DFTS (2015)
Keyphrases
- low power
- power consumption
- single chip
- low density parity check
- high speed
- vlsi architecture
- low power consumption
- power dissipation
- low cost
- cmos technology
- logic circuits
- digital signal processing
- gate array
- mixed signal
- real time
- vlsi circuits
- low complexity
- nm technology
- distributed video coding
- ldpc codes
- image sensor
- distributed source coding