Design of a 1-V 3-mW 2.4-GHz fractional-N PLL synthesizer in 65nm CMOS.

Yongho Lee Seungsoo Kim Hyunchol Shin

Published in: ISOCC (2017)

Keyphrases

power consumption
high speed
power supply
circuit design
cmos technology
clock gating
neural network
user interface
control system
embedded systems
low power
engineering design
frequency band
design considerations
single chip
power dissipation