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A 28-nm CMOS 7-GS/s 6-bit DAC With DfT Clock and Memory Reaching SFDR >50 dB Up to 1 GHz.
Georgi I. Radulov
Patrick J. Quinn
Arthur H. M. van Roermund
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2015)
Keyphrases
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clock gating
power consumption
power dissipation
random access memory
low power
nm technology
high speed
cmos technology
power reduction
low voltage
design considerations
analog to digital converter
clock frequency
frequency domain
memory requirements
low cost
fourier transform
flip flops
database