Hardware Implementation of Iterative Projection Aggregation Decoding for Reed-Muller Codes.
Marzieh Hashemipour-NazariKees GoossensAlexios Balatsoukas-StimmingPublished in: CoRR (2022)
Keyphrases
- general purpose
- hardware implementation
- decoding algorithm
- error control
- parity check
- efficient implementation
- software implementation
- error correcting
- fpga implementation
- signal processing
- ldpc codes
- hardware design
- low density parity check
- pipeline architecture
- fractal encoding
- hardware architecture
- error correction
- joint source channel
- field programmable gate array
- dedicated hardware
- image processing algorithms
- reed solomon
- parallel architecture
- turbo codes
- high speed
- reed solomon codes
- image transmission
- software engineering
- pipelined architecture
- real time
- image binarization
- low cost
- memory management
- belief propagation