A Novel Hardware Architecture for Low Power and Rapid Testing of VLSI Circuits.

Jiann-Chyi Rau Po-Han Wu Chia-Jung Liu

Published in: APCCAS (2006)

Keyphrases

vlsi circuits
low power
hardware architecture
power consumption
low cost
high speed
mixed signal
hardware implementation
hardware architectures
digital signal processing
logic circuits
power reduction
gate array
real time
cmos technology
low power consumption
image sensor
field programmable gate array
neural network