Fractional-N DPLL-Based Low-Power Clocking Architecture for 1-14 Gb/s Multi-Standard Transmitter.
Masum HossainWaleed El-HalwagyA. K. M. Delwar Hossain AurangozebPublished in: IEEE J. Solid State Circuits (2017)
Keyphrases
- low power
- high speed
- vlsi architecture
- power consumption
- low cost
- cmos technology
- mixed signal
- nm technology
- single chip
- low power consumption
- power dissipation
- high power
- vlsi circuits
- real time
- digital signal processing
- vlsi implementation
- wireless transmission
- logic circuits
- image sensor
- data flow
- signal processor
- power supply
- np complete