Performance Analysis of a Modified MAP Decoder Architecture for Low Power Dissipation.
S. ShiyamalaV. RajamaniPublished in: Circuits Syst. Signal Process. (2015)
Keyphrases
- low power
- vlsi architecture
- energy dissipation
- low cost
- power consumption
- high speed
- cmos technology
- nm technology
- low complexity
- single chip
- mixed signal
- vlsi circuits
- real time
- digital signal processing
- high power
- low power consumption
- low density parity check
- logic circuits
- wireless transmission
- signal processor
- vlsi implementation
- design methodology
- gate array
- power reduction
- design considerations