An 18.6Gb/s double-sampling receiver in 65nm CMOS for ultra-low-power optical communication.
Meisam Honarvar NazariAzita Emami-NeyestanakPublished in: ISSCC (2012)
Keyphrases
- ultra low power
- low power
- high speed
- cmos technology
- power consumption
- image sensor
- nm technology
- data acquisition
- information sharing
- low cost
- communication networks
- communication systems
- communication protocol
- sampling strategy
- physical layer
- silicon on insulator
- monte carlo
- circuit design
- solid state
- sample size
- delay insensitive