Hardware implementation of a modified SSD LDPC decoder.
A. RajagopalK. KaribasappaK. S. Vasundara PatelPublished in: Int. J. Comput. Aided Eng. Technol. (2021)
Keyphrases
- hardware implementation
- fpga implementation
- ldpc codes
- low density parity check
- signal processing
- distributed source coding
- efficient implementation
- software implementation
- euler number
- distributed video coding
- image binarization
- decoding algorithm
- dedicated hardware
- turbo codes
- image processing algorithms
- hardware design
- hardware architecture
- low complexity
- error correction
- parallel architecture
- real time
- field programmable gate array
- machine learning
- fpga device
- message passing
- rate distortion