Securing Hardware Accelerator during High-level Synthesis.
Dipanjan RoySabiya Jani ShaikSonam SharmaPublished in: HOST (2022)
Keyphrases
- high level synthesis
- parallel architecture
- parallel implementation
- field programmable gate array
- hardware implementation
- hardware and software
- low cost
- real time
- computing systems
- computer systems
- information security
- parallel processing
- hardware architecture
- image processing
- distributed memory
- design space exploration
- data processing
- shared memory
- probabilistic model
- bayesian networks