A Hardware-Efficient Feedback Polynomial Topology for DPD Linearization of Power Amplifiers: Theory and FPGA Validation.
Chak-Fong CheangPui-In MakRui Paulo MartinsPublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2018)
Keyphrases
- hardware implementation
- field programmable gate array
- real time
- low cost
- theoretical framework
- hardware architecture
- power reduction
- data acquisition
- user feedback
- massively parallel
- hardware design
- parallel architectures
- software implementation
- high power
- efficient implementation
- power consumption
- relevance feedback
- image processing