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Area efficient parallel decoder architecture for long BCH codes.
Yanni Chen
Keshab K. Parhi
Published in:
ICASSP (5) (2004)
Keyphrases
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reed solomon
error correction
parallel execution
multi processor
management system
low complexity
parallel programming
distributed processing
error control
image sequences
software architecture
parallel processing
shared memory
parallel implementation
decoding algorithm
fpga implementation