Login / Signup

Fault-Tolerant Techniques to Manage Yield and Power Constraints in Network-on-Chip Interconnections.

Anelise KologeskiCaroline ConcattoFernanda Lima KastensmidtLuigi Carro
Published in: VLSI-SoC (Selected Papers) (2012)
Keyphrases
  • fault tolerant
  • fault tolerance
  • interconnection networks
  • network on chip
  • distributed systems
  • load balancing
  • power consumption
  • routing algorithm
  • image processing
  • high speed
  • multistage